1. Field of the Invention
The present invention generally relates to the design of semiconductor chips and integrated circuits, and more particularly to a method of placing components of an integrated circuit design in a layout.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins, including information about the various components such as transistors, resistors and capacitors. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then run through a dataprep process that is used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to etch or deposit features in a silicon wafer in a sequence of photolithographic steps using a complex lens system that shrinks the mask image. The process of converting the specifications of an electrical circuit into such a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to repower gates (changing their sizes), insert repeaters (buffers or inverters), clone gates or other combinational logic, etc., so the area of logic in the design remains fluid. However, physical synthesis can take days to complete, and the computational requirements are increasing as designs are ever larger and more gates need to be placed. There are also more chances for bad placements due to limited area resources. Given a netlist N=(V, E) with nodes (vertices) V and nets (edges) E, a global placement tool obtains locations (xi, yi) for all the movable nodes, such that the area of nodes within any rectangular region does not exceed the area of cell sites in that region. Though some work has looked at general Steiner wirelength optimization, placers typically minimize the half-perimeter wirelength (HPWL) of the design. Modern placers often approximate HPWL by a differentiable function using a quadratic objective.
One placement technique that has proven to be a viable alternative to simulated annealing or top-down partitioning methods is known as force-directed placement. A force-directed placement tool essentially relies on two main operations: (a) a linear system solver operation that obtains a globally optimum solution for a given set of constraints and design objectives (this solution typically generates a result that has significant overlap among the cells), and (b) a spreading operation is performed to reduce the overlap among the cells by spreading their relative placement and thereby add additional “spreading” constraints to the result generated by the linear system solver operation. These two operations are carried out in an iterative manner to reduce overlap among the cells until a stopping criterion is met, such as when there is no appreciable reduction in the HPWL spread solution, when the average movements of modules due to spreading constraints converges, or when the average density of the cells with respect to a certain regular grid structure is smaller than a predefined threshold. The spreading operation does not actually move the cells, but only determines expected locations of the cells that provide a reasonable reduction in overlap. Once the spreading operation is performed to obtain expected locations, spreading forces are added to the design to reduce overlap among the cells. These spreading forces may be added by inserting pseudo pins and pseudo nets in the design.
Force-directed placers provide continuous trajectories for cell locations and are therefore particularly amenable to timing- and congestion-driven placement as well as physical re-synthesis. The SimPL algorithm is one example of a flat, force-directed global placer. It maintains a lower-bound placement and an upper-bound placement, and progressively narrows the displacement between the two to yield a final placement solution. The upper-bound placement is generated by applying lookahead legalization (LAL), which is based on top-down geometric partitioning and non-linear scaling. SimPL provides improvements in speed and solution quality while allowing easy integration with other optimizations.